Vertical Slit Transistor Based Integrated Circuits (VeSTICs): Overview and Highlights of Feasibility Study

In this note, the concept of Vertical Slit Transistor Based Integrated Circuits (VeSTICs) is introduced and its feasibility discussed. VeSTICs paradigm has been conceived in response to the rapidly growing complexity/cost of the traditional bulk-CMOS-based approach and to challenges posed by the nano-scale era. This paradigm is based on strictly regular layouts. The central element of the proposed vision is a new junctionless Vertical Slit Field Effect Transistor (JL VeSFET) with twin independent gates. It is expected that VeSTICs will enable much denser, much easier to design, test and manufacture ICs, as well as, will be 3Dextendable and OPC-free.